1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and more particularly to the semiconductor device in which a semiconductor layer is formed with a front-end insulating layer interposed between the semiconductor layer and an insulating substrate.
The present application claims priority of Japanese Patent Application No. 2006-101140 filed on Mar. 31, 2006, which is hereby incorporated by reference.
2. Description of the Related Art
For example, in an LCD (Liquid Crystal Display) device known as a representative display device, an active-matrix substrate on which a TFT (Thin Film Transistor) is formed is used as a driving device for a liquid crystal element. In the TFT, a semiconductor layer made of an amorphous silicon film, polycrystalline silicon film, or a like formed on an insulating substrate is employed as its active layer in which active regions such as a source region and a drain region are formed. Due to diversification of use of LCDs in recent years, it is required that the TFT to be used is multi-functional, scaled down, and made fine and further has a high reliability and/or high endurance.
As an insulating substrate for a TFT, a glass substrate is employed which is advantageous in terms of manufacturing costs, however, mixture of some kinds of impurities into the glass substrate at a stage of manufacturing is unavoidable to facilitate easy manufacturing and processing of the glass substrate. However, these impurities act on the semiconductor layer serving as an active region of the TFT and have such a bad effect as causes a change in threshold value which is an important factor of characteristics of the TFT, thus resulting in degradation of reliability of the TFT. Even a very small amount of boron or aluminum in particular mixed as such impurities therein exerts much influence on the characteristics of the TFT. To avoid this, prior to a process of forming the semiconductor layer on the glass substrate, a cleaning process is performed on the glass substrate, however, complete removal of these impurities is impossible.
A conventional TFT is disclosed in Patent Reference 1 (Japanese Patent Application Laid-open No. Hei 5-203982) or Patent Reference 2 (Japanese Patent Application Laid-open No. 2005-340280), which is capable of protecting a semiconductor layer against being affected by impurities contained in a glass substrate. FIG. 9 is a cross-sectional view of the conventional TFT disclosed, for example, in the Patent Reference 1. The conventional TFT 100, as shown in FIG. 9, includes an insulating substrate 101, a front-end insulating layer 102 formed on the insulating substrate 101, a semiconductor layer 103 formed on the front-end insulating layer 102, a source region 104 formed in one end of the semiconductor layer 102, a drain region 105 formed in another end of the semiconductor layer 102, a gate insulating film 106 formed on the semiconductor layer 103, a gate electrode 107 formed on the gate insulating film 106, an interlayer insulating film 108 formed on all surfaces thereof including a surface of the gate electrode 107, a source electrode 111 formed so as to be in contact with the source region 104 via a contact hole 109 obtained by forming a hole through the interlayer insulating film 108 formed on all surfaces thereof including a surface of the gate electrode 107, and a drain electrode 112 also formed as to be in contact with the drain region 112 via a contact hole 110 obtained by forming a hole through the interlayer insulating film 108.
According to the conventional TFT 100 having the configurations described above, the semiconductor layer 103 is formed with the front-end insulating layer 102 interposed between the semiconductor layer 103 and the insulating substrate 101 and, therefore, invasion of impurities into the semiconductor layer 103 is blocked and action of the impurities on the semiconductor layer 103 is suppressed. As a result, a change in threshold value of the TFT can be prevented.
However, the conventional TFT disclosed in the Patent Reference 1 has a problem. That is, even if the front-end insulating layer 102 is interposed between the semiconductor layer 103 and the insulating substrate 101, when various heat treatment processes are performed at stages of manufacturing the TFTs, impurities contained in the insulating substrate 101 are diffused, due to the heat treatment, into the front-end insulating layer 102 and the diffused impurities act on the semiconductor layer 103. In other words, in order to form, for example, the source region 104 and drain region 105, phosphorus (N-type impurity), boron (P-type impurity), or a like is implanted into the semiconductor layer 103 and, after that, processes to perform heat treatment at a comparatively high temperature of 300° C. or more such as an activating process to activate such impurities are repeated. As a result, if the insulating substrate 101 on which the semiconductor layer 103 is formed with the front-end insulating film 102 interposed between the semiconductor layer 103 and insulating substrate 101 is exposed to heat generated by the heat treatment for a long time, boron or aluminum diffuses from the insulating substrate 101 into the front-end insulating layer 102.
Then, when boron or aluminum diffuses into the front-end insulating layer 102 and gets near the semiconductor layer 103, characteristics of the TFT are made to change. There is a possibility that this phenomenon occurs due to action of boron or aluminum as a fixed charge in the front-end insulating layer 102. Boron or aluminum acts, when diffusing through the front-end insulating layer 102 and then reaching the semiconductor layer 103, as an acceptor and, as a result, a change in threshold value of the TFT occurs. This phenomenon becomes remarkable when the impurity has reached a neighboring portion of the semiconductor layer 103 located immediately below the gate electrode 107 or neighboring regions of the semiconductor layer 103 having an LDD (Lightly Doped Drain) structure or the semiconductor layer 103 having the LDD structure.
One possible method to solve the above problem is to lower temperatures to be used for heat treatment during the activating process described above to suppress the diffusion of boron or aluminum from the insulating substrate 101 into the front-end insulating layer 102. However, to lower the temperatures used for heat treatment during the activating processes leads to a failure in achieving its original purpose of the heat treatment, which causes negative factors such as a decrease in an activation rate, a breakdown voltage of gate insulating film, or a like. Therefore, even if the front-end insulating layer 102 is formed on the insulating substrate 101 as in the case of the TFT disclosed in the Patent References 1 and 2, it is impossible to avoid degradation in reliability of the TFT.